A hard disk writer/driver system requires a specialized electronic circuit to produce a signal in order to drive a writing inductor. The writer/driver electronic circuit launches short duration high voltage signals or a pulsed signal across the writing inductor. Based on a need to produce these high voltage signals, a writer/driver pre-amplifier is often included as a sub-system of a writer/driver electronic circuit. The response time of writer/driver pre-amplifier must be extremely fast for a high speed writing system. Complementary Metal Oxide Semiconductor (CMOS) technology based writer/driver pre-amplifier electronic circuits are conventionally used for such applications based on their response time as compared to NPN or bipolar transistor technology based circuits.
In specific applications, a pair of control signals are used. The first for a P-type Metal Oxide Semiconductor (PMOS) section of the circuit is generally referred to as positive boosting control signal. The second for an N-type Metal Oxide Semiconductor (NMOS) section of the circuit is generally referred to as a negative boosting control signal. Both the positive boosting control signal and the negative boosting control signal are most often represented as pulsed signals, retaining a specific voltage level V1 for a certain duration of time T1 and then switching to another voltage level V2 for another duration of time T2. The signals transition between two different voltage levels are often different for the positive boosting control signal and for the negative boosting control signal. For high speed writing systems, the two time durations T1 and T2 are very small.
The requirements for the presently employed boosting control signals include that they are asymmetric relative to one another. In order to generate the relatively asymmetrical positive and negative boosting control signals, an input signal is conventionally processed through separate electronic circuit components in a manner that the single input signal may be split into separate signals to generate the above-discussed asymmetry. A consequence of processing the input signal through separate electronic circuits to generate separate boosting control signals is that the two boosting control signals are subjected to differing time delays in processing. As a result, two boosting control signals are rendered asynchronous in a time domain.
The difference in the time delays that the two boosting control signals are subjected to during processing could be significant at high writing speeds. The asymmetric nature of the positive and negative boosting control signals, therefore, results in asynchronous signaling of the non-identical signal levels. A result of the presenting asynchronous asymmetric positive and negative boosting control signals to the writer/driver pre-amplifier electronic circuit may be the undesired effect of unequal common mode (CM) voltage at two output nodes, across which a differential output signal of the writer/driver pre-amplifier electronic circuit may be generated by combining the two boosting signals. As such, there may be CM voltage spikes in the output of a CMOS writer/driver pre-amplifier electronic circuit. These unwanted spikes are fed to the writing inductor resulting in unsatisfactory performance of the hard disk writer, and possible damage.
To better illustrate the situation described above, FIG. 1 schematically illustrates a high level simplified block diagram of an exemplary hard disk writing system 1000. As shown in FIG. 1, the system 1000 may include an input data source 1010 that may provide a data signal 1015 representing data to be written on a hard disk, and a number of intermediate components for processing the input data before the system generates a drive signal across the writing inductor 1110. These intermediate components may include, for example, a writing pulse signal generator 1020, the output 1025 of which may be input, in parallel, to a positive boosting control signal generator 1030 and a negative boosting control signal generator 1040. The outputs 1035, 1045 respectively of the positive boosting control signal generator 1030 and the negative boosting signal generator 1040 may be input to separate pulse signal shaping systems 1050, 1060, the outputs 1055, 1065 of which may subsequently be input to level adjusters 1070, 1080. The outputs 1075, 1085 of the level adjusters 1070, 1080, respectively, may be input to a writer/driver pre-amplifier 1090. The differential input pair 1093, 1097 of the writer/driver pre-amplifier 1090 may be input to an amplifier 1100, the output 1105 of which is input to a writing inductor 1110.
The data signal 1015 provided by the input data source 1010 may include logic levels and may already have been processed to make the data signal 1015 as true a copy of the data that was intended to be written on the hard disk that is possible. The data signal 1015 may be input to a writing pulse signal generator 1020 that may convert the logic levels in the data signal 1015 into a writing pulse signal 1025 at suitable voltage levels. The writing pulse signal 1025 may have several discriminating characteristics associated with it. These may include pulse signal transition time instants, a pulse signal transition high level, a pulse signal transition low level, a pulse signal rise time, a pulse signal fall time, a pulse signal duration, or a pulse signal duty cycle. Based on the specifications of the writing inductor 1110, one or more of the discriminating characteristics may be suitably set. For example, as the speed of writing increases the writing pulse signal duration may be reduced and accordingly the writing pulse signal rise time and the writing pulse signal fall time durations may also be reduced.
The writing pulse signal 1025 may be processed along two distinct processing paths. In order to perform very high speed writing and driving, the writing pulse signal 1025 ultimately crosses the writing inductor 1110 in a balanced manner. Two separate pulse signals may be generated, one each through separate distinct processing paths. The two different pulse signals include a positive boosting control signal 1035, via a positive boosting control signal generator 1030, and a negative boosting control signal 1045, via a negative boosting control signal generator 1040. The positive boosting control signal 1035 and the negative boosting control signal 1045 may be related to each other in the sense that as the positive boosting control signal 1035 may transition from a higher level to a lower level, the negative boosting control signal 1045 may transition from a lower level to a higher level and vice versa. The signals are, therefore processed to be generally asymmetric for reasons mentioned above and as will be discussed in greater detail below.
The processing paths may include related positive and negative boosting control signal generators 1030, 1040, that may generate pulse signal with suitable asymmetric transitions from one voltage level to another, pulse signal shaping system 1050, 1060 that may clean up the input signals 1035, 1045 to produce an output signals 1055, 1065 such that the output signals 1055, 1065 may have rise and fall times that are acceptable according to a pre-specified criterion. The output signals 1055, 1065 of the pulse signal shaping systems 1050, 1060 may be input to level adjusters 1070, 1080 such that output signals 1075, 1085 of the level adjusters 1070, 1080 may have suitable values of pulse signal transition high and pulse signal transition low levels. A need for level adjustment may arise because the subsequent processing block, writer/driver pre-amplifier 1090, may require input signals with a pre-specified value of transition levels.
The pair of inputs, positive boosting control signal 1075 and negative boosting control signal 1085 may be input to writer/driver pre-amplifier 1090 that may produce a pair of outputs 1093 and 1097. The writer/driver pre-amplifier 1090 may generate enough signal strength at the outputs 1093 and 1097 such that the outputs 1093 and 1097 may be effectively amplified through the amplifier block 1100, so that a short duration high voltage write pulse signal may be provided to the writing inductor 1110, in order that the writing process may be accomplished successfully.
FIG. 2 illustrates a simple schematic of a CMOS technology based hard disk writer/driver pre-amplifier electronic circuit 2000. A PMOS transistor PM2100 and an NMOS transistor NM2200 have inputs I2100 and I2110, respectively. In one cycle of operation, both the inputs I2100 and I2110 are the boosting control signals 2300 and 2350, respectively, having pulse signal characteristics and being applied substantially simultaneously. The signal at input I2100 makes a transition from the voltage level VDD to VSS, wherein VDD>VSS, and then makes transition back from the voltage level VSS to VDD. The duration of the pulse signal at input I2100 is the length of time for which the input I2100 remains at the level VSS, which is equal to TP. The input I2110 makes a transition from the voltage level VEE to VSS, wherein VEE<VSS, and then makes transition back from the voltage level VSS to VEE. The duration of the pulse signal at input I2110 is the length of time for which the input I2100 remains at the level VSS, which has a value substantially close to TP. Both the transitions, VDD to VSS in I2100 and VEE to VSS in I2110 are intended to occur in a synchronous manner substantially simultaneously. Similarly, both the transitions, VSS to VDD in I2100 and VSS to VEE in I2110 are intended to occur in a synchronous manner substantially simultaneously. In the same mode of operation, the inputs I2210 and I2200 to the PMOS transistor PM2200 and NMOS transistor NM2100 have DC values 2400 and 2450, respectively.
Subsequently, in a next cycle, the roles would be reversed with the input I2210 of PMOS transistor PM2200 and input I2200 of NMOS transistor NM2100 having the pulse signal characteristics and being applied substantially simultaneously identical to the inputs I2100 and I2110 in the depicted cycle. Similarly, the inputs I2100 and I2110 to the PMOS transistor PM2100 and NMOS transistor NM2200 have DC values identical to the inputs I2200 and I2210 in the depicted cycle.
During the depicted cycle of operation, the input I2100, which in a simplified form is the gate terminal of PM2100, is a boosting control signal 2300 of a duration Tp that sends the output node U2100 high and hence is described as a positive boosting control signal. Substantially simultaneously, during the same depicted cycle of operation, the input I2110, which in a simplified form is gate terminal of NM2200, is a boosting control signal 2350 of a duration very close to Tp that sends the output node U2200 low and hence is described as a negative boosting control signal. The net result of this operation is an enhanced differential output between nodes U2100 and U2200. Similarly, during a next cycle of operation, the net result would be an enhanced differential output between nodes U2200 and U2100.
The two boosting control signals 2300 and 2350 are pulse signals that ideally should transition exactly identically in time. However, in practice, they may occur substantially simultaneously. In addition, the two control inputs 2400 and 2450 are boosting control signals that ideally should transition exactly identically in time. However, in practice they may also occur substantially simultaneously.
The electronic circuit of FIG. 2 suffers from drawbacks that the two boosting control signals 2300 and 2350 having opposing transitions as well as having higher and lower transition levels that are generally different. The opposing transitions are such that as one makes a transition from a lower level to a higher level, the other makes a transition from a higher level to a lower level and vice versa. Conventionally, this means that the boosting control signals 2300 and 2350 must be generated through different electronic circuits with the attendant drawbacks, as discussed above. Consequently, the two input signals I2100 and I2110 experience different delays based on individual circuit elements being different.
It should be noted that individual device characteristics, such as, for example parasitic capacitance, may play a significant role in determining a signal delay through an individual device. Individual device delays may vary with the distinct, operating voltage levels. The delays are generally cumulative and not easily predicted or modeled, thus resulting in unwanted output characteristics when the signals are combined, one example being the CM voltage spikes discussed above. Often, processing delays through the devices are non-linear, are functions of the operating voltage levels. Consequently, the two boosting control signals, although ideally needing to be substantially synchronous in time domain are rendered, to some extent, asynchronous.
In high speed writing, where the hard disk writer electronic circuit must respond in sub-nanosecond time intervals, different delays of even several tens of picoseconds between a positive boosting control signal 2300 and a negative boosting control signal 2350 may be adverse to the operation of the system. The hard disk writing process, for example, involves launching a short time duration high voltage pulse signal across a writing inductor, which needs high current through the writing inductor for satisfactory operation. To generate the needed high current through an amplifier 1100, as shown in FIG. 1, requires switching equivalently high currents through the PM2100 and NM2100 pair as well as PM2200 and NM2100 pair. A challenging task is to accomplish this magnitude of current switch cleanly in less than a few tens of picoseconds.
CM voltage spikes degrade the writing process and the amount of degradation is more pronounced with higher writing speeds. The resulting degradation may impact error free data storage. In order to retain the retrieved data integrity at a satisfactory level, advanced signal processing and/or coding techniques may be required, resulting in an increase in the cost, size and the power consumption of the electronic circuit that performs writing and/or retrieving information in the hard disk system.